cslc
generates a cycle based C++ simulator. C++ libraries contain the
simulation engine and classes used to build the design infrastructure
in the C++ simulator automatically. The
clsc translates the CSL input files into a C++ design hierarchy and
interconnect. CSL vector specifications are translated into C++ vector
writers which are automatically connected to the associated unit's
ports. CSL architectural state specifications are translated into
architectural state writers which are automatically connected to the
associated memory state element. Currently the vector and architectural
state writers generate files. Future version will connect to sockets
which will connect to the automatically generated testbench. The C++
simulator has a command shell which is used to control the execution of
the simulator and to inspect the design using print statements, watch
points, and break points. Currently the user is responsible for
flattening the logic into single evaluation cones. This is a practice
that is currently used widely in the industry by simulator writers. A
cone checker will be implemented in future versions of the compiler.
The cone checker will verify that the user C++ logic does not contain
logic loops with in pipelines which break the cycle base simulation
model.
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